Advances in semiconductor manufacturing technology have led to the integration of billions of circuit elements, such as transistors, on a single integrated circuit (IC). In order to integrate increasing numbers of circuit elements onto an integrated circuit it has been necessary to reduce the dimensions of the electronic devices (e.g., a metal-oxide-semiconductor (MOS) transistor).
A typical packaged integrated circuit unit includes a die in or on which the integrated circuit is formed and a package substrate on which the die is mounted. An interconnect structure connects the terminals of the die from the integrated circuit in the die to the terminals of the package, which can be further connected to other components through a circuit board. The package may be directly mounted on the circuit board, or through a socket or an interposer.
Semiconductor manufacturers desire an understanding of the stress-induced performance and reliability effects for these scaled electronic devices. Destructive techniques are typically used to measure stress levels in the die. Strain gauge rosettes have been considered for placement on the die, but are not sufficiently accurate or robust at these smaller scales. Thus, there are no current non-destructive methods to accurately determine stress levels in semiconductor devices.